In integrated circuits (ICs), various devices such as a memory device and a logic device are configured to achieve a desired function. During fabrication of a memory device, e.g., an embedded third generation SuperFlash® (ESF3), and a logic device, the thickness of a gate electrode layer, e.g., a polysilicon layer, suitable for forming a word line (WL) of the memory device is non-uniform across the edge and center regions of the memory array region, e.g., a memory cell (MCEL) region. A portion of the gate electrode layer and gate stack at the edge of the memory array region is undesirably removed during chemical mechanical polishing (CMP) resulting in a sloped profile. Further, the thickness of the remaining gate electrode at the center region of the memory array region after an etch back (EB) process is non-uniform, e.g., the remaining gate electrode within the WL is lower than that at the edge of the memory array region, adversely impacting yield.
A need therefore exists for methodology enabling the formation of a uniform WL over the memory cell (MCEL) region.